TI is using vertically integrated engineering teams with the goal of realizing a $10 4G chip operating at 100 MHz with 10 million gates and memory.
Researchers at KAIST have announced that they have developed the worlds smallest transistor with a channel length of 3 nanometers. This would enable the development of terabit memories and processor speeds of 100GHz without the use of exotic materials such as carbon nanotubes or information processing within molecular materials.
As reported by the EE Times, Japan’s Toppan Photomasks apparently brought in Sean Connery, or someone that looked like him, for a reception at the SPIE Microlithography event in San Jose. (SPIE, spy, 007…get it?) It’s still not certain whether the man was the genuine article, but if he were I suppose it’s a step up from literally dancing for Japanese whiskey.
The EE Times article does a good job of going over the progress of realizing immersion lithography, but I suppose it could be summed up in one simple word.